Abstract: Code Generation of Time Critical Synchronous Programs on the Kalray MPPA Many-Core architecture

[Sophie Quinton]

Title: Code Generation of Time Critical Synchronous Programs on the Kalray MPPA Many-Core architecture

Authors:
Amaury Graillat (VERIMAG / Kalray, France)

Abstract:
Embedded software as found in aircraft, nuclear power plants and cars, is said to be critical since bugs can have hazardous consequence to human lives. A bug can be behavioral or temporal for instance a result too late is a bad result. Hence, we talk about time-critical software. The Worst-Case Response Time is the bound of this result computation. Critical codes are often generated from formal languages such as the Dataflow Synchronous Languages (SCADE, Lustre, Esterel, etc). Today the critical systems are still running on old single-core processors since theses processors are quite simple and make the computation of the WCRT easy. But, the growing demand for computational power in avionics and automotive makes the single-core processors limited. Multi-core processors offer enough computational power but are often too complex to allow computation of the
WCRT. Hence, many-core processors are promising because they offer high computational power thanks to numerous but very simple cores.

Our purpose is to parallelize and implement a Dataflow Synchronous program written in SCADE on a many-core processor. Nodes are statically scheduled on the cores to enhance temporal predictability. As the communications are in shared-memory, the solution makes the interferences as predicable as possible to allow the computation of the WCRT. We use a prototype of the SCADE compiler that allows developer to specify the nodes
of the program that must be executed in parallel. With this information, the compiler generates new blocks that communicate through data channels. A channel is composed of a data structure containing the data transferred between the blocks and special macros to write and read in this structure.

The execution platform is composed of 16 cores and a shared-memory divided into 16 banks such that access on a bank has no interference on the timing of access of another bank. According to the mapping information given by the developer, a node is executed on a core and its code stored in the corresponding memory bank. A sequencer allows several nodes to be executed sequentially one a core. Channels are implemented in a Remote Write manner, i.e., the result of a node in written in the memory banks of the destination nodes. To make the interference prediction easier for each node, two releases are defined: a release for execution, and a release to write the result.

We have implemented a code generator for the Kalray MPPA Bostan many-core SoC that takes the output of the SCADE compiler and the mapping and timing information provided by the developer, to generate C code using the Kalray low level libraries. We applied our study to ROSACE, an open source case-study of a flight controller. It is composed of an altitude controller and an environment simulator. We parallelized the altitude controller on one cluster using 5 cores. The environment simulation was located
on a second cluster communicating through the network-on-chip.

[amaury]

Here are the slides of the presentation.

WATERS2016_rendu.pdf

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